User1580871742356367
Occasional Contributor
Occasional ContributorEMIF controller and DDR4
Like to confirm who's programming the DDR4 MMR registers.
The Memory controller engine alone(without SW or SW (e.g. uboot etc.) ? Thanks.
Forum Discussion
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Sir,
I believe that the timing parameter setting is at the tRFC.
tRFC is refers to the Refresh Cycle Time where the amount of delay after a refresh command before an activate command can be accepted by the memory.
Thanks.
Adzim
