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LNagy2's avatar
LNagy2
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4 years ago

E-Tile XCVR PHY Gearbox 64/66 mode

Hello community, I would be interested on more details on the "Gearbox 64/66" mode of the E-Tile XCVR PHY IP https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_etile_...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI,


Pls see my reply below.


1. How is the 80 bits parallel data interface mapped in this mode ?

  • Kindly refer to mapping table (Table 33. 80 Bit Data Native PHY IP Double-width TX/RX Ports, page 63)

2. "You must use data_valid signals on both the TX and RX directions." Where are these data_valid signals mapped on the interface of the core ?

  • valid signal = parallel_data[68]

3. It is possible to use the PHY in a 66 ratio serdes mode, meaning we feed 66 bits at the parallel data interface on each clock cycle while using the div66 clock option to drive the core interface? See attached screenshot.

  • Yes. in NativePHY IP, you need to first checked "enable tx pma div66 clock" and "enable rx pma div66 clock" in TX PMA and Rx PMA tab
  • Then in NativePHY IP -> core interface tab, Tx clocks option and Rx clock option
  • Enable clkout2 port and set the clock source to div66


Thanks.


Regards,

dlim


  • LNagy2's avatar
    LNagy2
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello dlim,

    thanks for the quick reply. I had to set also the tx_clkout/rx_clkout to half-rate.

    With this setup I got a parallel data interface running at lane rate / 64 , that means I need to deassert valid each 33th cycle.

    Is there a setup where I can have a parallel interface running at lane rate/66 meaning the 'valid' can stay high all the time ?

    Thank you,

    Laszlo