Forum Discussion
E-Tile frequency constraints
Hi,
I've a question regarding the E-Tile transceiver and their constraints.
I would like to implement different data rates which I have already tested successfully using the reconfiguration interface.
Now I'd like to ask if it's necessary to create a constraint for the minimum and maximum frequency.
My intention would be to instantiate the E-Tiles with a lower data rate and create constraints for the minimum and maximum frequency used for RX/TX_out_clock.
I already tried it with the create_clock constraint to create it with their periods but obviously the values are truncated.
Can I specify ps or fs instead of ns for the clock period?
Another possibility would be:
Should I specify the highest data rate and the lower ones will be possible without timing violations, too?
Which 'strategy' would be the better one to avoid any issues with the E-Tiles during operation?
Best regards,
Michael
Hi,
If you observe issue trying to constrain the output clock ie cannot find in tech map, would you mind to help opening a new Forum case and let me know the case. I will help to route to our timing team to better assistance. Thank you.
18 Replies
- CheepinC_altera
Regular Contributor
Hi,
As I understand it, our timing team is currently assisting you in the new case. We shall continue to follow up with you in the new case. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.