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Altera_Forum's avatar
Altera_Forum
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16 years ago

Dual Port RAM

hi. i try to store sine wave into dual port RAM. However , the output of RAM, q is 1 cycle slower. when i count, i already include 1 cycle for output registered. May i know why? i change the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

When clock trigger, store_sin is 0 due to delay of fsin_o. So, the DRAM, save the 0 instead of -98 at address 3.

I disagree because when address 3 is read, the q value is -98 as it should be