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Altera_Forum
Honored Contributor
16 years agoDual Port RAM
hi. i try to store sine wave into dual port RAM. However , the output of RAM, q is 1 cycle slower. when i count, i already include 1 cycle for output registered. May i know why? i change the...
Altera_Forum
Honored Contributor
16 years agoI see q changes -98 1 cycle after read address 3m w/o output registered.
Read address 3 is 2 cycles after write address 3, was it supposed to be 1 cycle later instead of 2?