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Altera_Forum's avatar
Altera_Forum
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16 years ago

Dual Port RAM

hi. i try to store sine wave into dual port RAM. However , the output of RAM, q is 1 cycle slower. when i count, i already include 1 cycle for output registered. May i know why? i change the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It looks like you are registering the read address so it takes 1 cycle to clock the internal ram address, then the read data is valid on the second cycle, in effect a 1 stage pipeline.

My design is not ready yet for simulation, so please post the results if you remove the external register. My whole design depends on the 1 cycle access so I am very interested in your results!!!!!