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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dual port RAM shared between Nios and async interface

Hi all, I want to upgrade an existing system and I wonder if anyone can give me hints. I have a board with CIII device with Nios and an external Analog Device DSP: both Nios and DSP need to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Altera is moving away from that so I wouldn't expect many or any Qsys components to use the synthesis translate on/off functionality. Qsys generates synthesis and simualtion files into seperate directories which is a much cleaner approach.