Dual port RAM shared between Nios and async interface

Thank you for replying again

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Maybe you have to assert the wait signal for the host processor before you get the wait from the avalon

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I think this is not a problem. My host processor can add a fixed number of wait cycles before it starts polling waitrequest signal.

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and maybe you have to assert the wait for the host processor longer then the avalon wait is asserted (especially for reads from the host). This depends on the timing of your host processor.

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This would not be a problem, too. I can add minimal glue logic to generate the reuiqred delay

Regards