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Altera_Forum
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15 years ago

Dual port RAM shared between Nios and async interface

Hi all, I want to upgrade an existing system and I wonder if anyone can give me hints. I have a board with CIII device with Nios and an external Analog Device DSP: both Nios and DSP need to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Cris,

the avalon wait signal should be enough, but it can be a bit more complicated than just using this signal as wait signal for your host. Maybe you have to assert the wait signal for the host processor before you get the wait from the avalon and maybe you have to assert the wait for the host processor longer then the avalon wait is asserted (especially for reads from the host). This depends on the timing of your host processor.