Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dual port RAM shared between Nios and async interface

Hi all, I want to upgrade an existing system and I wonder if anyone can give me hints. I have a board with CIII device with Nios and an external Analog Device DSP: both Nios and DSP need to a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

I think there are two points to consider if you do accesses to the main avalon bus from your host processor.

1. You have to synchronize the host processor accesses to your avalon clock domain.

2. Your host processor should have some kind of ready/wait/TA signal.

--- Quote End ---

Yes, this was implied in the question.

I'm aware of these requirements.

Thank you