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Altera_Forum
Honored Contributor
Honored ContributorDSP Builder to ModelSim
Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error: # ** Error: (vsim-3817) Formal port "clk" decl...
Altera_ForumHonored Contributor
Honored ContributorBtw, have you tried compiling your DSP Builder design in Signal Compiler yet? Judging from the error statement, there is a chance that your IP cache folder got corrupted (it happens from time to time, especially when you migrate from one version of DSP Builder to another)...
I would suggest the following: 1. Delete the existing IP cache folder(s) in your computer... Go to C:\Documents and Settings\<User Name>\ --> Inside that folder, you should see a .altera.quartus folder 2. Delete that folder and restart your DSP Builder... see if you still see the same error... Best of luck.
