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Altera_Forum's avatar
Altera_Forum
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12 years ago

dsp builder-quartus project

hello, i have created a project for multichannel duc, and able to generate quartus project file. the top module is entity duc is port ( channel : in std_logic_vector(7 d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If it is fixed frequency then I don't want the tool to generate processor interface. If it does set interface inputs to zero and ignore its outputs