dsp builder-quartus project

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If you want a processor to update your coefficients then this bus is generated(data, address, write...). If you don't want update then set your filter block to constant coeffs and the bus will disappear.

By the way channel input is not needed ! as it is not connected internally as far as I know.

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hello,

i changed the read/write mode into constant, for all the filters and NCO. but still it is showing the same in NCO entity...

component working_duc_nco is

port (

busin_d : in std_logic_vector(31 downto 0);

busin_a : in std_logic_vector(15 downto 0);

busin_w : in std_logic_vector(0 downto 0);

xin_c : in std_logic_vector(7 downto 0);

xin_v : in std_logic_vector(0 downto 0);

xin_p_0 : in std_logic_vector(23 downto 0);

xin_p_1 : in std_logic_vector(23 downto 0);

xin_p_2 : in std_logic_vector(23 downto 0);

xin_s_0 : in std_logic_vector(0 downto 0);

xin_s_1 : in std_logic_vector(0 downto 0);

xin_s_2 : in std_logic_vector(0 downto 0);

sinout_0 : out std_logic_vector(17 downto 0);

sinout_1 : out std_logic_vector(17 downto 0);

sinout_2 : out std_logic_vector(17 downto 0);

cosout_0 : out std_logic_vector(17 downto 0);

cosout_1 : out std_logic_vector(17 downto 0);

cosout_2 : out std_logic_vector(17 downto 0);

ncoout_v : out std_logic_vector(0 downto 0);

ncoout_c : out std_logic_vector(7 downto 0);

clk : in std_logic;

areset : in std_logic;

h_areset : in std_logic

);

end component;

what change should i have to make ?