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Altera_Forum's avatar
Altera_Forum
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15 years ago

DSP builder IP generator error

Hi, I am using DSP builder 9.1, 10.0. I added the FFT mega core to my simulink model the regular IP generator GUI. When I double click it again, I rceive the following message in MATL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks a lot for you help.

It is working now. The problem was that some VHDL files in the model were not compiled. when I used the command "alt_dspbuilder_refresh_HDLimport" in Matlab command window, it compiled all the VHDL files of the design and it worked.

Thanks again for you help.

Thanks

Ahmed