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Altera_Forum
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13 years ago

DSP Builder Hardware in the Loop / FPGA I/O pins

Hello, I’m having a lot of trouble getting an output in the FPGA pin using a HIL (Hardware in the Loop) block using Altera Block set library in Simulink.

I made the design in the Simulink and compile and program without a problem, but when I replace it to the HIL block the inputs and outputs don’t get out of the FPGA

Thanks for any help

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I´m using a Cyclon IV E FPGA and have the same problem. Did you solve it?

    I tried the examples out of the DSP Builder handbook, but non of them worked on my device/system...