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Altera_Forum
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13 years ago

DSP Builder Hardware in the Loop / FPGA I/O pins

Hello, I’m having a lot of trouble getting an output in the FPGA pin using a HIL (Hardware in the Loop) block using Altera Block set library in Simulink. I made the design in the Simulink and com...
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Altera_Forum
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13 years ago

I´m using a Cyclon IV E FPGA and have the same problem. Did you solve it?

I tried the examples out of the DSP Builder handbook, but non of them worked on my device/system...