Driving FPGA -> Host DMA with PCIe (hard IP in Cyclone IV)?

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_Which_ DMA status register?

I'm not using the DMA controller, my logic drives a DMA tansfer directly.

This has to be able to read the DMA status but I can't see anything in the

PCIe user guide about a 'finished the transfer' register.

Nial.

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Bump.

Has no-one else driven DMA transfers over the PCIe core from their own logic?

How do you know when you can write the next burst?

Thanks for any pointers,

Nial.