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Honored Contributor
Honored ContributorDoes SDR SDRAM controller have pin restrictions?
Hello. I'm using the Altera Single Data Rate SDRAM controller for a NIOS2 Cyclone4E design. Does the SDR SDRAM controller have any pin restrictions like the DDR controllers have, or can I ...
Altera_ForumHonored Contributor
Honored ContributorThe only thing I did take care of was the SDRAM clock output. As this usually connects directly to a PLL, you should use the dedicated input and output pins for the PLL you select.
My Quartus had problems deciding where to put the PLL, so I had to manually assign it to PLL2 (Cyclone3, Quartus 9.1SP2).
