Forum Discussion
Deshi_Intel
Regular Contributor
5 years agoHI,
The reference design can be generated insides low latency 10G MAC IP directly. The reference design will contains both MAC + PHY IP together.
You can also refer to below design example doc as reference.
Thanks.
Regards,
dlim
BQi
Occasional Contributor
5 years agoWhich page? I can not find the reference design has both 1GE/10GE support.