Hi, I have build a system which has NIOS II, DDR SDRAM controller, On-Chip RAM, UART,DMA Controller. My program memory is DDR SDRAM. I have connected DMA controller between DDR SDRAM and On-Chip Memory. I have written a program to transfer data from SDRAM to on-chip memory, before transfering the data from DDR SDRAm i write an incremental data pattern into DDR SDRAM. the program executes but i am not seeing the pattern data into my On-Chip RAM why i don't know? is logically i am correct to DMA the data from program memory i.e. DDR SDRAM to On-chip RAM?? Thanks, Bhupesh

Make sure the contents written to memory before the DMA transfer are not cached. See the software handbook for the Nios II processor for more details on cache bypassing.

Hi BadOmen, I am using NIOS s version of CPU, i think it does not have data cache. The address range for SDRAM is 00000000h to 01FFFFFFh before SDRAM there is an clock crossing bridge it's address range is 02000000h to 03FFFFFFh. My program code size is 40Kbytes. I write a data pattern of 64 words starting at address 00100000. My on-chip RAM is at address 05000000h. After DMA when i check at 00100000h address i see the data pattern. but when i see at 05000000h i see some garbage value, before DMA value at 05000000h was 0h. Any idea why is going wrong? thanks, bhupesh

If your sdram has an adress range from 00000000h to 01FFFFFFh and your clock crossing bridge starts at 02000000h assuming only the sdram is behind that bridge, then it is correct that this bridge has an adress range from 02000000h to 03FFFFFFh as you just have to add both adress values. your problem is that you write to 00100000 but there is no sdram, as you must take the bridge into account, you have no memory between 00000000h to 01FFFFFFh i bet it will work if you change 00100000 to 02100000

Hi MSchmitt, Yes my SDRAM is behind clock crossing bridge. I tried with 02100000 insted of 00100000 but no sucess. I will try to tap some signal n see... thanks

now i am a bit confused. if your sdram is behind the bridge and that bridge is between nios and dma the nios and dma must have the same adress to gain access. so i wonder why you see your pattern at 00100000 instead of 02100000 could you post a screenshot of the sopc to see the connection between nios, dma bridge and sdram ?

DMA Transfer Issue | Altera Community

14 Replies

Altera_Forum
Honored Contributor
16 years ago
Thanks MSchmitt,

It is working :)

I made those changes u sugestted at different places of the code.

Thanks,
Bhupesh
Altera_Forum
Honored Contributor
16 years ago
fine, nice to read.

so i assume that the system.h still holds the start adress of the ddr but that is not the start adr nios and dma sees due to the bridge offset.

maybe some altera gurus can explain how altera recommends to use these adresses from system.h or it is supposed to be used.
Altera_Forum
Honored Contributor
16 years ago
Hi MSchmitt,

you r write the nios & dma does not seems to be looking DDR SDRAM address, insted they see a bridge address. In system.h the DDR SDRAM & Bridge address where set to same i.e bridge address. I think i was making some mistake while passing the address.

I will try to change the code with the base address and update with the result.

thanks,
bhupesh
Altera_Forum
Honored Contributor
16 years ago
Hi

I am surprised to see that in my program this line of code works IOWR(DDR_Write_Address,0,data);

and this one does not give me the correct result
IOWR(DDR_SDRAM_BASE,DDR_Write_Address,data);

this remains same for both
iprintf("Written %08x to address %08x \n", data, DDR_Write_Address);
DDR_Write_Address += 4;
data += 1;

in first line of code DDR_Write_Address = base address which works :)

in second line of code DDR_Write_Address = offset address which does not give me result i want :mad: :mad:

any input ....idea???

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DMA Transfer Issue

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