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Altera_Forum
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16 years ago

DMA Transfer Issue

Hi, I have build a system which has NIOS II, DDR SDRAM controller, On-Chip RAM, UART,DMA Controller. My program memory is DDR SDRAM. I have connected DMA controller between DDR SDRAM and On-Chi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi BadOmen,

I am using NIOS s version of CPU, i think it does not have data cache.

The address range for SDRAM is 00000000h to 01FFFFFFh before SDRAM there is an clock crossing bridge it's address range is 02000000h to 03FFFFFFh.

My program code size is 40Kbytes. I write a data pattern of 64 words starting at address 00100000.

My on-chip RAM is at address 05000000h.

After DMA when i check at 00100000h address i see the data pattern. but when i see at 05000000h i see some garbage value, before DMA value at 05000000h was 0h.

Any idea why is going wrong?

thanks,

bhupesh