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Honored Contributor
Honored ContributorDMA read using PCIe hard core
We design DMA controller which implement the data transmission between the PCIe module(which is PXI device) and general PC(OS is Windows XP). The Quartus version is 11.0, and the FPGA is EP4SGX70HF35...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Does the native endpoint could implement the DMA read? Or we should initiate a rootpoint? Or we configure the TLP in a wrong way? --- Quote End --- PCIe end-points can implement both DMA reads and writes, you do not need to implement a root-complex (in fact you cannot if the board is to be plugged into a peripheral slot). You must have an error in your logic. I'd recommend simulating your design, but Altera's support for PCIe simulation is not particular good. I haven't tried recently (Quartus 13.x), so perhaps it has improved. Hopefully others on the forum will comment. Cheers, Dave
