Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DMA Controller Core and data alignment

Hi, I have a problem with the DMA Controller Core which I can't understand. My system has a NIOS/f core (with unused MPU, 4Kb caches, 32 bytes data cache line size) connected to a SDRAM, a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The problem seems to be located in the SDRAM controller, which does not like odd local start burst addresses (with, in my case, burst length=2).

As the performance loss is not excessive without bursts, I will just skip them for the time being.

P9