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Altera_Forum
Honored Contributor
16 years agoDMA and PCIe
Hi, I have SOPC system with PCIe, DDR2 and DMA. BAR0 is connected to CRA of PCIe at base 0x1000_0000. BAR1 is connected to DMA control port slave at offset 0x100. DMA's read-master is linked t...
Altera_Forum
Honored Contributor
15 years agoHi,
We're not using Nios for DMA at the moment, so no DMA API (if that's what you're asking) and DMA registers are directly accessed by the host. The host talks to PCIe BARs (and thru BARs to DMA) by invoking a custom driver for RTX - a real-time extension of windows. The writeaddress for DMA in SOPC must be actual physical addr on the RTX driver (not virtual addr) and must be contiguous. Usually there are APIs at driver-level to do this and you may not have to do it yourself. Depending on the non-paged pool size of your windows host, you may not be able to get 1:1 mapping of the entire DDR2 on you PCIe endpoint (on SOPC) and the host's memory. So multiple DMA xfers may be necessary between DDR2 and host. Look for "Avalon-MM-to-PCI Express Address Translation" in PCI Express Compiler User Guide to understand how xlation process works. Hope this helps, -swguy