Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI'll keep that modular SGDMA design in mind, but for now I really want to be things as easy as possible. I also knew this Accelerated FIR Design, but because I'm rather unexperienced in HDL I wanted to do the same just in DSP Builder.
Can you give me any hints here? For a simple proof of concept/workflow I made a DMA test model in Simulink which should do memory to memory transfers using these MM Master templates within HDL import blocks (finally integrating the fir in simulink shouldn't be a problem at all). But either I connected the blocks in a wrong way or I'm not using the right 'export' method out of simulink, because a short test within a small nios-driven system didn't work. I'm at home now, but tomorrow I will attach the simulink model. For an experienced person it is probably quite obvious what might be wrong. Regards, Sebastian