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New ContributorDisplayPort Sink | 2 Pixel per Clock Video | Output not correct
Hi,
I am using a DisplayPort IP core as sink, two 2.7 GB lanes, 1920 x 1080.
It works perfectly with 1 pixel per clock.
For a new project I need video data with even and odd pixels output
So ...
HI,
You can learn more about expected video data interface output from DP user guide doc (chapter 6.5.4, page 102)
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf
- You may also want to monitor rxN_vid_valid signal assertion to detect the active video
Like wise you can also try generate DIsplayPort example design and monitor the vide traffic transaction.
Thanks.
Regards,
dlim
