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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DisplayPort Only Connects to Windows not Linux

Hi, I am trying to use the DisplayPort sample design on a Stratix 10 board. I have implemented the exact sample project from Intel with the Bitec daughter card but am seeing some issues. When I plu...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Daniel,


I understand that your system setup is like below :

------------

system setup

------------

GPU -> DP cable -> Bitec DC rev11 -> custom board (S10 SX280 FPGA) -> same Bitec DC rev11 -> DP cable -> Monitor


Lets' stick with using Intel FPGA DP default example design for debug purpose. Don't integrate with additional design block for now to keep thing simple.

  • Quartus version : v19.2 (I am thinking v19.2 since you mentioned it started support Bitec DC rev11 as compared to not supported v19.1)
  • DP IP bpc : 8 bpc
  • DP data rate setting : 5.4G (HBR2)
  • GPU mode : turn on GPU mode is fine


After that, share with me the MSA log for Nvidia GTX 660Ti running in Linux.


For my side, I will try to check for some transceiver Rx channel internal status signal that you can add to signal_tap to aid in debug purpose.


Thanks.


Regards,

dlim


DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

I removed my entire project and only used the sample project (v19.2) with my pinout.

With both Win7 and Win10 I am seeing the same issue I had before where LT goes and goes and goes until the NIOS/UART gives out (unresponsive).

I was able to grab this MSA dump right before it stopped:

------------------------------------------
------ TX Main stream attributes -----
------------------------------------------
--- Stream 0 ---
MSA lock : 0
VB-ID : 19 MISC0 : 00 MISC1 : 00
Mvid : 138E5 Nvid : 8000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
--- Stream 1 ---
MSA lock : 0
VB-ID : 00 MISC0 : 00 MISC1 : 00
Mvid : 0000 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
------------------------------------------
-------- TX Link configuration -------
------------------------------------------
Lane count : 4
Link rate : 5400 Mbps
------------------------------------------
------ RX Main stream attributes -----
------------------------------------------
--- Stream 0 ---
VB-ID lock : 0 MSA lock : 0
VB-ID : 19 MISC0 : 00 MISC1 : 00
Mvid : 0100 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
--- Stream 1 ---
VB-ID lock : 0 MSA lock : 0
VB-ID : 00 MISC0 : 00 MISC1 : 00
Mvid : 0000 Nvid : 0000
Htotal : 0000 Vtotal : 0000
HSP : 0000 HSW : 0000
Hstart : 0000 Vstart : 0000
VSP : 0000 VSW : 0000
Hwidth : 0000 Vheight : 0000
CRC R : 0000 CRC G : 0000 CRC B : 0000
------------------------------------------
-------- RX Link configuration -------
------------------------------------------
CR Done: F SYM Done: 0
Lane count : 4
Link rate : 5400 Mbps
BER0 : 7FFF BER1 : 08A8
BER2 : 072A BER3 : 17A6

I am now compiling with v20.2 to see if it works any better.

Thanks,

Daniel