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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DisplayPort Only Connects to Windows not Linux

Hi, I am trying to use the DisplayPort sample design on a Stratix 10 board. I have implemented the exact sample project from Intel with the Bitec daughter card but am seeing some issues. When I plu...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI Daniel,


I drop you a private message.


I hope you can see it. Let me know if there is an issue in viewing private message as Intel forum system just got upgraded.


As for lower video resolution control - you just need to set Intel DP IP datarate to HBR2 (5.4G). No other RTL change is required.


As for the MSA screen shot. yup. Just type "s" and hit "enter" key in NIOS II shell terminal. I can see you already have it in the end of your previous working Nvidia 660 Ti Win 7 log file. I would like to see the MSA log for the failing case.


Thanks.


Regards,

dlim


  • DZuck1's avatar
    DZuck1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi dlim,

    I was able to see the private message. I will respond to that directly.

    I will work on recompiling with the lower resolution and printing out the MSA tomorrow. From my memory, the VB-ID and MSA lock are both 0 and the BER is a high number for all of the lanes.

    Thanks,

    Daniel

  • DZuck1's avatar
    DZuck1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    I will test out the compilation with the lower link rate (HBR2).

    When I try to dump out the MSA from the NIOS when plugged into Linux I sometimes run into a problem where the NIOS has become unresponsive. The DP Debug AUX trace stops printing mid line and does not respond to any commands.

    I was able to print out this MSA dump:

    ------------------------------------------
    ------ TX Main stream attributes -----
    ------------------------------------------
    --- Stream 0 ---
    MSA lock : 0
    VB-ID : 19 MISC0 : 20 MISC1 : 00
    Mvid : 138E5 Nvid : 8000
    Htotal : 0000 Vtotal : 0000
    HSP : 0000 HSW : 0000
    Hstart : 0000 Vstart : 0000
    VSP : 0000 VSW : 0000
    Hwidth : 0000 Vheight : 0000
    CRC R : 0000 CRC G : 0000 CRC B : 0000
    --- Stream 1 ---
    MSA lock : 0
    VB-ID : 00 MISC0 : 00 MISC1 : 00
    Mvid : 0000 Nvid : 0000
    Htotal : 0000 Vtotal : 0000
    HSP : 0000 HSW : 0000
    Hstart : 0000 Vstart : 0000
    VSP : 0000 VSW : 0000
    Hwidth : 0000 Vheight : 0000
    CRC R : 0000 CRC G : 0000 CRC B : 0000
    ------------------------------------------
    -------- TX Link configuration -------
    ------------------------------------------
    Lane count : 0
    Link rate : 0 Mbps
    ------------------------------------------
    ------ RX Main stream attributes -----
    ------------------------------------------
    --- Stream 0 ---
    VB-ID lock : 0 MSA lock : 0
    VB-ID : 19 MISC0 : 00 MISC1 : 00
    Mvid : 0100 Nvid : 0000
    Htotal : 0000 Vtotal : 0000
    HSP : 0000 HSW : 0000
    Hstart : 0000 Vstart : 0000
    VSP : 0000 VSW : 0000
    Hwidth : 0000 Vheight : 0000
    CRC R : 0000 CRC G : 0000 CRC B : 0000
    --- Stream 1 ---
    VB-ID lock : 0 MSA lock : 0
    VB-ID : 00 MISC0 : 00 MISC1 : 00
    Mvid : 0000 Nvid : 0000
    Htotal : 0000 Vtotal : 0000
    HSP : 0000 HSW : 0000
    Hstart : 0000 Vstart : 0000
    VSP : 0000 VSW : 0000
    Hwidth : 0000 Vheight : 0000
    CRC R : 0000 CRC G : 0000 CRC B : 0000
    ------------------------------------------
    -------- RX Link configuration -------
    ------------------------------------------
    CR Done: 0 SYM Done: 0
    Lane count : 1
    Link rate : 1620 Mbps
    BER0 : 17F0 BER1 : 11A4
    BER2 : 076C BER3 : 0DD8

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      HI dlim,

      When I was trying out the different versions of Quartus (19.1, 19.2 and 20.2) I can see that 19.1 does not support the Bitec rev 11 FMC card but 19.2 does. However, the I2C setup commands for the retimer chip in the NIOS code is significantly different between 19.2 and 20.2. v20.2 also implements an MC_monitor and other new functions that v19.2 did not use. Which version of the I2C commands should I be using?

      Thanks,

      Daniel

      • DZuck1's avatar
        DZuck1
        Icon for Occasional Contributor rankOccasional Contributor
        6 years ago

        Hi dlim,

        I am working on the v20.2 compile. In the meantime, I turned off AUX debug printout in software to ensure that I would be able to get my MSA dump printouts (UART otherwise can get stuck).

        I am attaching two traces. One has multiple MSA dumps for Win7 and one has multiple MSA dumps for Win10. Both show that the LT seems to finish and then lose lock (CR and SYM transition to F and then back to 0). I have hooked up some of my LEDs to the the user_led_g[2:0] which are used to show dp_rx_vid_locked and dp_rx_link_rate. I am seeing that the dp_rx_vid_locked LED is always on and the dp_rx_link_rate LEDs are constantly toggling.

        Would there be any benefit in testing an RX only design? Do you know where in the RX PHY I should be placing signalTap?

        Thanks,

        Daniel