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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DisplayPort Only Connects to Windows not Linux

Hi, I am trying to use the DisplayPort sample design on a Stratix 10 board. I have implemented the exact sample project from Intel with the Bitec daughter card but am seeing some issues. When I plu...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Daniel,


Sorry, I am back. I have been reading your recent update and looks like it's not just simple Wins vs Linux issue anymore.

  • 660 TI (Win 7) - pass with video output
  • 660 TI (Ubuntu) - failed with no video output ?
  • RTX 6000 (Win 10) - failed with no video output ?
  • RTX 6000 (CentOS) - failed with no video output ?


  1. For Quartus v20.2 compilation error issue
  • This looks like some Quartus internal error which is totally new issue here.
    • Does it happen in your own design only or also affect DisplayPort example design ?
  1. For no video output debug
  • I don't have your exact graphic card spec but google search review some info below
    • GPU (Nvidia GTX 660Ti)
      • DP version ? (suspect it's DP v1.2)
      • 4096x2160 (including 3840x2160) at 60Hz supported over Displayport
    • GPU (Nvidia RTX 6000)
      • DP v1.4, support 4 DP connector port
      • 4096x2160 @ 120Hz, 5120x2880 @ 60Hz
    • Dell monitor U2718Q
      • DP v1.2
      • 3840 x 2160 at 60 Hz
    • Nvidia RTX 6000 never works could be due to it's too advance and it maybe exercising some new DP feature that's not supported by Dell Monitor that's just supporting DP v1.2.
      • For instance, DP v1.2 only support till HBR2 (5.4Gb/s). So, it doesn't make sense to configure Intel FPGA DP IP to use HBR3 (8.1Gb/s) setting.
      • I also don't think this DELL monitor support adaptive sync feature. Pls disable it in GPU card setting. Anyway, Intel FPGA DP IP doesn't support Nvidia G-sync feature, we only support AMD adaptive sync feature but it needs to be special enabled in Intel FPGA DP IP
    • You are also stressing both Nvidia 660 TI GPU and Dell monitor since their max video resolution capability is also just 4kp60
      • Not sure if you had try out below debug option ?
      • Changed Intel FPGA DP IP data rate setting from 8.1Gb/s to 5.4Gb/s
      • Try out different bit per colour (bpc) setting in Intel FPGA DP IP. Also do you know what's the bpc setting in GPU card ?
      • Thanks for sharing the AUX log but it's very hard to read without the decoder aid. Do you manage to dump the MSA log file for the failure case as well ?


Thanks.


Regards,

dlim


DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi dlim,

I am happy that you are back and the forum is back up and running.

When I compile the sample design in Quartus v20.2 it does not have this issue. My project started in v19.1 then migrated to v19.2 and then v20.2. The project never had any compilation issues remotely similar to what I am seeing in v20.2.

I tried enabling Adaptive Sync in the NIOS code, per the sample design user guide, but it had no effect.

I am not sure why the dell monitor's version of DP plays a role in the FPGA's version of DP. The setup I test with is either:

  • monitor<-GPU->FPGA
  • GPU->FPGA->Monitor

The issue is between the GPU and the FPGA.

I tried recompiling the design with the only the lower rates enabled (2.7 Gbps and below) but I am not sure that I did it right. Is the only change i need to make the DP RX IP Core drop down in Platform Designer or do I need to make RTL changes as well (param to bitec reconfig module, etc.).

As for the MSA log file, are you referring to the print out on the screen when the 's' key is pressed?

Thanks,

Daniel