DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

Hi,

Your understanding of general calibration process is correct that they are trying to calibrate certain offset value internally but my concern is without the clock, I am not sure whether the transceiver channel can be reverted to use back the default offset setting.

I worry the whole state machine design is stuck pending for clock source.

In your earlier debug signal capture ,

• rx_reconfig_busy = 1
• This is status signal to indicate completion of transceiver calibration process. It should de-assert low once calibration completed.
• But right now looks like it's waiting for the missing clock and the whole calibration process is stuck forever

In proper operation, once calibration completed then only transceiver channel will be released from reset stage (gxb_rx_analogreset = 0, gxb_rx_digitalreset = 0)

I am not sure which calibration bit setting that you refer to but I am aware of only one register bit that we used to "trigger re-calibration process in FPGA user mode", not to skip calibration process

Regards,

dlim