DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

Hi,

Transceiver reconfiguration process itself is a complicated process so I don't have easy way to explain to you.

1. To learn more about it - you can refer to C10 GX transceiver PHY user guide doc (chapter 6) that I shared with you in earlier post
2. To look at actual design implementation example, bitec_reconfig_alt_c10.v is the reconfig controller example design that do all the magic trick. It's that complicated as you can see in the design file itself.
3. For DP design implementation, you only touch on Transceiver reconfiguration process during below 2 phases (I believed below operation are controlled by bitec_reconfig_alt_c10.v)

• During FPGA initial power up where you configure DP IP to operate at certain transceiver data rate
  • Whenever there is a need to change transceiver data rate, for instance DP link training process

The reset controller IP that I mentioned to you is below design module in rx_phy_top.v

• gxb_rx_reset gxb_rx_reset_i (
  • .reset (reset | dp_rx_xcvr_reset | rx_restart_100),
• You can signal_tap these 3 dependency reset OR signals to find out which one is causing the trouble and make necessary design changes

Thanks.

Regards,

dlim