DisplayPort at non GPU mode on Cyclone 10 GX and Quartus pro 20.1

Hi Michael,

Ok, I understand your confusion now.

Just to clarify, those transceiver reconfiguration bus are not GPU port and has nothing to do with DisplayPort GPU mode.

• These are just transceiver NativePHY IP Avalon MM port exposed to user design to allow user to perform dynamic reconfiguration process to change transceiver data rate
• How the dynamic reconfiguration control coding is done is really up to user itself. It can be in the form of RTL state machine or NIOS CPU C- code design
• You can refer to chapter 6 of below doc for explanation of transceiver dynamic reconfiguration process
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf

In C10 GX DP example design, the dynamic reconfiguration control RTL state machine coding design is located in bitec_reconfig_alt_c10.v and xcvr_reconfig_arbiter.sv as you mentioned.

• The MIF file is prebuild dynamic reconfiguration file for ease of transceiver data rate switching.
• For example : mif file location
• <DP example design>\rtl\rx_phy\gxb_rx\altera_xcvr_native_a10_xxx\synth\reconfig

The difference between DP IP Rx GPU mode on/off is as below

• GPU mode on : user has flexibility to control DP DPCD register space initialization in software like CPU C-code
• GPU mode off : DP DPCD register is hardcoded in DP Sink IP

So whether DP Sink IP GPU mode is off or on, it shouldn't affect your transceiver channel connection. I visualize the system design connection as below

• DP Sink IP <-> Transceiver Rx NativePHY IP <-> additional dynamic reconfig design

Thanks.

Regards,

dlim