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JHill1's avatar
JHill1
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

direct instantiation of altera_mf_components IP from VHDL

When moving up from Intel/Altera 17 to 22 I am noticing a trend that maybe instantiation of altera_mf_components IP directly from within VHDL is no-longer supported, or will be supported in the futu...
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JHill1's avatar
JHill1
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

From my perspective, the use of VHDL generics for configuring the IP is actually the more modern, and not an older, approach for configuring device specific an d or proprietary features, and is more tightly integrated with HDL. Use of GUI tools is certainly easier for beginners. but the heavy lifting is actually done in text based HDL. Likewise, only from my perspective, TCL is an outdated and archaic language.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
7 months ago
As far as I understand, existing libraries like altera_mf are not removed, but they are not available to map the hardware of newer FPGA series, e.g. Stratix 10. This is primarily due to the complexity of these devices, not because someone considers the interface method as antiquated.

I remember when moving from altpll to altera_pll IP with Cyclone V, it was effectively impossible due to increased complexity to configure it according to IP user guide, you needed to generate the configuration by Megawizard and copy it to your HDL.