Forum Discussion
What's happening here is that the FIR needs 25x24 multiplications. On classic Cyclone devices, the widest native multiplier is 18x18 so DSP Builder needs to split the multiplication into multiple parts. This isn't the case for other families, which have 27x27 and/or 36x36 multipliers available. DSP builder splits the multiplication into 17-bit chunks and recombines the result. Effectively, it implements a 34x34 multiplier. The output of the 34x34 multiplier is 68 bits wide. Unfortunately, this is too wide for the simulation model used by the FIR compiler, which is restricted to 64-bit data paths. (This restriction does NOT apply to user-built systems, which use a different simulation model.) The result of this is that the Simulink simulation results for the FIR are incorrect. The generated hardware actually works properly, which means that the Modelsim simulation results will be correct but mismatch against the expected output (which is generated from the incorrect Modelsim results). We're working on it ...