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Altera_Forum
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11 years ago

Design using TSE ethernet mac megafunction : Modelsim simulation issues

Hello,

I am using the Triple-Speed Ethernet MegaCore Function on my design. I've used the .cmp file generated to instanciate the core. When i want to simulate the design with modelsim (using my own testbench, NativeLink and modelsim-altera 10.1e starter edition) i get the following error :

# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Protected: /top_tx_tb/dut_top_wrapper/u_bloc_mac/i_tse_fifoless_mac_0/U_TOP_XFIFO/genblk2/U_RGMII/the_rgmii_out1 File: nofile# FATAL ERROR while loading design

does anyone knows how to fix it or where it comes from ?

Thanks a lot in advance.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    [EDIT]

    Acutally my modelsim-altera version is a starter version and (if I understand) can't simulate mix HDL language. And i am wrinting in vhdl and the TSE IP is writing in verilog.

    So i've added all altera libraries to my full modelsim version and when i want to simulate the IP i have the folloing errors :# ** Error: C:/Users/giol/Desktop/altera_cpt/bloc_mac_testbench/testbench_vhdl/bloc_mac_sim/bloc_mac.vhd(1056): (vopt-1130) Port "tx_egress_timestamp_request_valid" of entity "altera_eth_tse_fifoless_mac" is not in the component being instantiated.

    #

    # ** Error: C:/Users/giol/Desktop/altera_cpt/bloc_mac_testbench/testbench_vhdl/bloc_mac_sim/bloc_mac.vhd(1056): (vopt-1130) Port "tx_egress_timestamp_request_fingerprint" of entity "altera_eth_tse_fifoless_mac" is not in the component being instantiated.

    #

    # ** Error: C:/Users/giol/Desktop/altera_cpt/bloc_mac_testbench/testbench_vhdl/bloc_mac_sim/bloc_mac.vhd(1056): (vopt-1130) Port "tx_etstamp_ins_ctrl_ingress_timestamp_96b" of entity "altera_eth_tse_fifoless_mac" is not in the component being instantiated.

    #

    # ** Error: C:/Users/giol/Desktop/altera_cpt/bloc_mac_testbench/testbench_vhdl/bloc_mac_sim/bloc_mac.vhd(1056): (vopt-1130) Port "tx_etstamp_ins_ctrl_ingress_timestamp_64b" of entity "altera_eth_tse_fifoless_mac" is not in the component being instantiated.

    [...] and more

    To simulate i am using Quartus with NativeLink which create me a file.do that i'm using with modelsim.

    Do you have any ideas ?