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Altera_Forum
Honored Contributor
17 years agoDesign IP Core of SPI
I 'm a student, I have a excercise " Design IP Core of SPI", so I begin learing Verilog for it. So, I don't know about SPI block diagram, interface, timing ... Have anyboy can help me ? And give me s...
Altera_Forum
Honored Contributor
17 years agohttp://en.wikipedia.org/wiki/serial_peripheral_interface_bus
Have fun. Jake