OABBA1New Contributor6 years agoDesign contains X blocks of type combinational node,However, device contains only X I am using a cpld that contain 40 block but my design have 288 block, there is a way to optimise the design without changing the device thank you
KhaiChein_Y_IntelRegular Contributor6 years agoHi,May I know if you have any updates?Thanks.Best regards,KhaiY
Recent DiscussionsCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsCyclone V CAN triple samplingSolvedR_Tile PCIEAgilex 7 I F-Tile Direct PHY: example TB doesn't workSolvedWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?