Debugging PCIe DMA transfer example design

Hi VenTing,

The all change I made is in the "API.cc". file, instead of creating random number and sending that to DDR4, I retained only reading part of the code (I mean write DMA is disabled and only have read DMA), I am just curious that is this the thing I am suppose to do? If not what are the potential changes that we should make?

Also, I would like to cross-check that during the Signal Tap capturing of the modified design, whether the Read DMA API is not suppose to run from host computer? (I mean to generate the trigger Avalon-MM read from the design (I mean from the unmodified part of the design) to the FiFO: I suspect the absence of this signal to FIFO cause no data from data generator (while running Signal Tap). Do you have any suggestion how to create those signals? Pls let me know if my question is not clear.

I really would like to have little bit more time to provide updates on https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507. Thanks for the understanding

Regards

SE