Debugging PCIe DMA transfer example design

Hi VenTing,

I ran the DMA read test and could not verify that we could read data that is being written to FIFO. Just a question, as the Signal Tap does not show the data flow to FIFO when it connects to the DMA design (as I mentioned in the last message) should be expect the DMA read to work?

I and currently I am trying to follow https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfer-example-design-for-Arria/m-p/1564164/highlight/true#M28507 and will update you.

Thank you

Regards

SE