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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Debugging PCIe DMA transfer example design

Hi, I would like to have your continued support on this thread. Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfe...
Pcie
Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Ven Ting,

I would like to check if you could recreate the error I am seeing.

Also I could see the compilation errors go away when I add nodes to the signals (from the screenshot you send... also see the screenshot `Capture_nodes_suggested.PNG) attached ) you suggested to my stp file. May I know why you suggested ctrl_amm_0 to add? Is it just for testing the compilation error I am seeing? Also, I am curious is it illegal to add nodes at address signals ?

Also in signalTap GUI, some nodes (eg: signals of ctrl_amm_0 ) looks unassigned. (picture attached) is it something normal?

Also do you have any suggestion on which nodes I can add to the stp file to visualize the data flow through my modified design (to test if the data generator created data goes to the DDR4 memory element correctly and then I can read that through PCIe DMA transfer from a host computer?). As a first step, I would like to visualize the data from data generator to DDR4, Any suggestion from your end to choose the signals to add nodes?

Regards

Sijith