Forum Discussion
3 Replies
- NurAida_A_Intel
Frequent Contributor
Hi @LChen23 ,
Thank you for joining this Intel Community.
Memory CAS latency setting= additive latency (AL) + the CAS latency (CL).
This parameter specifies the number of clock cycles between the read command and the availability of the first bit of output data at the memory device. The value is depends on the memory device selected; you need to refer to the memory datasheet for details.
Hope this helps.
Thanks
Regards,
Aida
- LChen23
New Contributor
I find it in Datasheet. When enable BID ,the CL may change to 22,or 23… Best Regard 陈亮 18017280310
- NurAida_A_Intel
Frequent Contributor
Hi,
Glad to know. 😊
Regards,
Aida