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Altera_Forum
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12 years ago

DDR3 SDRAM Unimemphy issue with qsys design

Hi there, I am beginner with DDR3 and try to integrate DDR3 SDRAM(MT41J128M16) with NIOS.My qsys design is having NIOS,DDR3 SDRAM Controller,JTAG UART and interconnect bridges. The issue is t...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Moving out of the SoC section so that you'll have people who know this answer see the post.

To be honest I'm not sure what that message means but I have ignored it many times and never had an issue. I suspect what it's trying to say is that the model being generated for the memory controller is functional only and so if you connect it to the timing memory model then bad things could happen.

Make sure you go through this document if you have not already done so if you plan on simulating code running on Nios II: http://www.altera.com/literature/an/an351.pdf