Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

DDR3 SDRAM Controller - issues caused by enabling the Efficiency Monitor !!!

Hi guys :) Another thread about the DDR3 SDRAM Controller with UniPHY... Used Quartus version is 13.1 SP1. I have built and run a memory test design with QSYS with the aim to do some la...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi again,

I placed the "Altera Avalon-MM Efficiency Monitor and Protocol Checker" in my QSYS Design, et voi lá, it is now possible to create a memory efficiency statistic.

Now I have to write a programm which allows to make resonable statements, according to throughput, latency and efficiency. Currentely I am running a March -C mem test and some pattern transfers with a DMA on the RAM.

Finally I want to be able to give a prediction about the real-time ability of the Controller.

Kind regards,

Roland