DDR3 SDRAM Controller - issues caused by enabling the Efficiency Monitor !!!

Hi All!

So problem solved... Yeah not really it is a known issue:

Q: Efficiency Monitor Not Usable With Arria V or Cyclone V Hard Memory Interface - Solution ID: fb107818; Not yet fixed!

Workaround / Fix

The workaround for this issue is to use Qsys to generate the external memory interface IP without the Efficiency Monitor, and then generate the Efficiency Monitor separately. You can then enable the Efficiency Monitor for your interface by connecting the Avalon interfaces manually.

This issue will be fixed in a future release.

Q: IP Generation Fails When Both Efficiency Monitor and Ping Pong PHY Enabled - Solution ID: fb158297

Workaround / Fix

The workaround for this issue is as follows:

In Qsys, manually instantiate your UniPHY-based external memory interface IP with Ping Pong PHY enabled and the Efficiency Monitor and Protocol Checker disabled.

Instantiate two copies of the Efficiency Monitor and Protocol Checker and connect them to the avl_c0 and avl_c1 interfaces of the UniPHY IP.

This issue will be fixed in a future version.

I hope others facing the same problem will now be able to find the reason a bit faster!

Solution is just to instantiate the Performance Monitor: "Altera Avalon-MM Efficiency Monitor and Protocol Checker" between the Data_master of the Nios, in my case, and the Slave Port of the SDRAM Controller.

I let you know if this solution leads to the good results.

Au revoir.

Roland