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Altera_Forum
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12 years ago

DDR3 Performance changes with different pinout

I have proven FPGA code in a Stratix IV GX that uses the NIOSII, Altera Video Suite IP components, and DDR3 Uniphys for the NIOS and Video buffering. On a previous board design, we were able to achi...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Although the board design is different, the FPGA device is the same. The pin-out of the FPGA is different.