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Altera_Forum
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11 years ago

DDR3 Performance changes with different pinout

I have proven FPGA code in a Stratix IV GX that uses the NIOSII, Altera Video Suite IP components, and DDR3 Uniphys for the NIOS and Video buffering. On a previous board design, we were able to achi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

Are you using different FPGA device? Previously which FPGA device are you using for DDR3 UniPHY interface?