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Altera_Forum
Honored Contributor
Honored ContributorDDR3 Native to Avalon-MM conversion
I have a system, wherein user logic is interfaced to DDR1 SDRAM Controller using native interface in Cyclone 2 device. The project was built in Quartus 11.1 and when we generate the DDR1 IP, either A...
Altera_ForumHonored Contributor
Honored ContributorThe cyclone V has built in DDR3 memory controller(s). If that's what you are talking about, using them is documented in the Cyclone V and Quartus handbooks. There is also the memory interface toolkit (which I've not used). You need to remove your Cyclone 2 memory controller and add the Cyclone V.
