Usually the 2nd rank of a DIMM would be mirrored, so for:
1. Controller for 1 DIMM of dual rank configuration:
Mirror Addressing Option in the Uniphy Megafunction GUI would be set to a value of 10 (Rank1 - Rank0)
2. Controller for 2 DIMMs of dual rank configuration:
Mirror Addressing Option in the Uniphy Megafunction GUI would be set to a value of 1010 (DIMM1,Rank1 - DIMM1,Rank0 - DIMM0,Rank1 - DIMM0,Rank0)
As I understand it, the purpose for address mirroring is that the DRAM ICs on the back of the DIMM module are mirrored from the ICs on the front. Rather than the memory module provider having to criss cross all of the address lines on the PCB for the back side DRAM ICs, the controller will do the address swapping in the FPGA when writing to the back side DRAM ICs.