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Altera_Forum
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13 years ago

DDR3 IP with Uniphy PLL_AFI_CLK timing closure problems

Reposting this from General Discussion. ===== Hello, I'm experiencing some problems compiling a project that uses a DDR3 IP with UNIPHY on an ARRIA V FPGA. I'm getting critical warnings...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

By my thinking the Arria V timing models are still only preliminary, so I guess for the moment you'll just have to ignore those warnings.