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Altera_Forum
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13 years ago

DDR3 IP with Uniphy PLL_AFI_CLK timing closure problems

Reposting this from General Discussion. ===== Hello, I'm experiencing some problems compiling a project that uses a DDR3 IP with UNIPHY on an ARRIA V FPGA. I'm getting critical warnings...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi xslik,

Did you find something, I got the same problem. I'am using the Quartus 12.1 to compile a design with DDR3 using the Hard memory IP :

pll_afi_clk warning in the setup time in the TimeQuest Timing Analyser reports.

Does anybody can help us ?

Thanks